neosyn-fpga-mcp — Claude Code MCP server for FPGA development
Connect an AI coding agent to the C⏚ FPGA toolchain to check source code, run simulations, and produce Verilog for hardware development.
claude mcp add --env CG_JAR=<CG_JAR> --transport stdio neosyn-fpga-mcp -- uvx neosyn-fpga-mcpWhat neosyn-fpga-mcp does
neosyn-fpga-mcp exposes C⏚ compiler and verification functions to AI agents over MCP. The agent can inspect compiler diagnostics, simulate a design, and generate Verilog files. Its cg_synth tool runs synthesis through Yosys, returning findings that help identify constant-folded logic or inferred latches.
The server works alongside cg_context.md, a language reference pack covering C⏚ types, ports, structures, and other language details. For a new design, cg_scaffold creates a compiling, self-checking starting structure with unfinished logic sections. A practical workflow is to compile first, simulate the design, and then inspect its synthesis results.
You need Python 3.10+, Java 17 or newer on PATH, and a C⏚ compiler JAR configured through CG_JAR. Install Yosys on PATH to use cg_synth; iverilog is needed when selecting the Icarus Verilog simulator. The bytecode simulator comes with the commercial distribution, which also requires a licence file configured through NEOSYN_CG_LICENSE or stored at the extension's default location.
What it helps with
- Inspect C⏚ source code and resolve compiler diagnostics
- Simulate hardware behavior and check output values
- Generate Verilog files for an RTL workflow
- Detect constant-folded logic or inferred latches during synthesis
- Create a self-checking scaffold for a task, FSM, or stream
Example prompts for the agent
- Check this C⏚ source with
cg_checkand fix the reported compiler issues. - Run
cg_simulateon this hardware design and verify its outputs across test cycles. - Generate Verilog with
cg_generate_verilog, then inspect the synthesis results usingcg_synth.
How to install neosyn-fpga-mcp
Platform CLI
claude mcp add --env CG_JAR=<CG_JAR> --transport stdio neosyn-fpga-mcp -- uvx neosyn-fpga-mcpReplace <…> with your own values. uvx runs the command named after the package; if the README names another one, use uvx --from neosyn-fpga-mcp <command>
Platform CLI
codex mcp add neosyn-fpga-mcp --env CG_JAR=<CG_JAR> -- uvx neosyn-fpga-mcpReplace <…> with your own values. uvx runs the command named after the package; if the README names another one, use uvx --from neosyn-fpga-mcp <command>
Config file
{
"mcpServers": {
"neosyn-fpga-mcp": {
"command": "uvx",
"args": [
"neosyn-fpga-mcp"
],
"env": {
"CG_JAR": "<CG_JAR>"
}
}
}
}Replace <…> with your own values. uvx runs the command named after the package; if the README names another one, use uvx --from neosyn-fpga-mcp <command>
Config file
{
"servers": {
"neosyn-fpga-mcp": {
"type": "stdio",
"command": "uvx",
"args": [
"neosyn-fpga-mcp"
],
"env": {
"CG_JAR": "<CG_JAR>"
}
}
}
}Replace <…> with your own values. uvx runs the command named after the package; if the README names another one, use uvx --from neosyn-fpga-mcp <command>
Platform CLI
gemini mcp add -e CG_JAR=<CG_JAR> neosyn-fpga-mcp uvx neosyn-fpga-mcpReplace <…> with your own values. uvx runs the command named after the package; if the README names another one, use uvx --from neosyn-fpga-mcp <command>
Step by step, with commands for each platform: How to add an MCP server to Claude Code, Codex, Cursor, VS Code, Gemini CLI and more
Questions about neosyn-fpga-mcp
How do I install neosyn-fpga-mcp in Claude Code?
Register the server with claude mcp add neosyn-fpga-mcp -- uvx neosyn-fpga-mcp. Then configure the compiler JAR using claude mcp add --env CG_JAR=<CG_JAR> --transport stdio neosyn-fpga-mcp -- uvx neosyn-fpga-mcp.
What does neosyn-fpga-mcp do?
It gives an AI agent MCP tools for compiling and simulating C⏚, generating Verilog, and checking synthesis. The returned diagnostics provide concrete feedback for revising hardware code.
Which dependencies does neosyn-fpga-mcp require?
The setup requires Python 3.10+, Java 17 or newer, and a C⏚ compiler JAR configured with CG_JAR. Yosys is needed for cg_synth, while iverilog is required when using the Icarus Verilog simulator.
