fpga — Claude Code skill: what it does, how to install
SystemVerilog and Vivado hardware design guidelines covering timing closure, AXI interfaces, resource savings, and testbench verification.
npx skills add Mindrally/skills --skill fpga -a claude-codeWhat fpga does
The skill injects guidelines for FPGA engineering with Vivado and SystemVerilog directly into the agent. It guides the model to build modular architectures, use interface blocks, and favor synchronous resets across design modules.
The instructions focus on timing closure using XDC constraint files and static timing reports. It outlines ways to infer block RAM via reg [], optimize lookup tables, configure AXI and DMA burst transfers, and debug designs with the Integrated Logic Analyzer.
Because the practices center on Vivado tooling and SystemVerilog, designers targeting other EDA suites or pure VHDL workflows will need to adjust the constraints and syntax manually.
What it helps with
- resolve setup and hold timing violations using XDC constraints
- implement safe clock domain crossings with FIFOs or handshakes
- configure AXI stream or memory-mapped channels with DMA bursts
- build self-checking SystemVerilog testbenches with assertions
Example prompts for the agent
- Help me pipeline this SystemVerilog module to fix timing violations reported by Vivado.
- Design a clock domain crossing module using a handshake protocol.
- Write an assertion-based testbench to verify read transactions on our AXI bus.
How to install fpga
1Skills CLI (Vercel)
npx skills add Mindrally/skills --skill fpga -a claude-code2Manually: put the files in place
~/.claude/skills/fpga/SKILL.mdCopy the whole skill folder; for one project use .claude/skills/fpga/
1Skills CLI (Vercel)
npx skills add Mindrally/skills --skill fpga -a codex2Manually: put the files in place
.agents/skills/fpga/SKILL.mdFor all projects use ~/.agents/skills/
1Skills CLI (Vercel)
npx skills add Mindrally/skills --skill fpga -a cursor2Manually: put the files in place
.cursor/skills/fpga/SKILL.mdCursor also reads .agents/skills/ and .claude/skills/
1GitHub CLI
gh skill install Mindrally/skills fpga2Manually: put the files in place
.github/skills/fpga/SKILL.md1Skills CLI (Vercel)
npx skills add Mindrally/skills --skill fpga -a gemini-cli2Platform CLI
gemini skills install https://github.com/Mindrally/skills --path fpgaManually: put the files in place
.devin/skills/fpga/SKILL.mdThe legacy .windsurf/skills/ path still works
Skills CLI (Vercel)
npx skills add Mindrally/skills --skill fpga -a opencodeClaude.ai
Zip the folder and upload it in Settings → Capabilities → Skills
Step by step, with commands for each platform: How to install skills in Claude Code: five ways
Questions about fpga
How to install fpga in Claude Code?
Run npx skills add Mindrally/skills --skill fpga -a claude-code in your terminal.
What does the fpga skill do?
It directs the AI to follow FPGA design practices, including static timing analysis, module structuring, and power optimization in Vivado.
Which hardware description languages are supported?
The guide centers on SystemVerilog syntax, particularly interface blocks and assertion verification.
Source text
SKILL.md · Apache-2.0
--- name: fpga description: FPGA development guidelines covering Vivado, SystemVerilog, timing closure, AXI interfaces, and hardware optimization. metadata: maintainer: Mindrally source: https://github.com/Mindrally/skills --- # FPGA Development You are an expert in FPGA development with Vivado, SystemVerilog, and hardware design optimization. ## Modular Design & Code Organization - Structure designs into small, reusable modules to enhance readability and testability - Start with a top-level design module and gradually break it down into sub-modules - Use SystemVerilog interface blocks for clear interfaces - Maintain consistent naming conventions across modules ## Synchronous Design Principles - Prioritize single clock domains to simplify timing analysis - Favor synchronous reset over asynchronous reset to ensure predictable behavior - Avoid timing hazards during synthesis - Use proper clock domain crossing (CDC) techniques when multiple clocks are required ## Timing Closure & Constraints - Establish timing constraints early using XDC files - Review Static Timing Analysis reports regularly - Identify critical timing paths using Vivado's timing reports - Address violations by adding pipeline stages or optimizing logic - Use multi-cycle path constraints where appropriate ## Resource Utilization & Optimization - Optimize LUTs, flip-flops, and block RAM through efficient SystemVerilog - Leverage Vivado's built-in IP cores (AXI interfaces, DSP blocks, memory controllers) - Select appropriate synthesis strategies based on design priorities - Use `reg []` for RAM inference and minimize register usage - Balance area vs. speed optimization based on requirements ## Power Optimization - Implement clock gating to reduce dynamic power consumption - Use Vivado's power-aware synthesis - Set power constraints for low-power applications - Minimize switching activity in non-critical paths ## Debugging & Simulation - Write detailed, self-checking testbenches covering typical use cases and edge cases - Use SystemVerilog assertions for verification - Run behavioral and post-synthesis simulations - Use Integrated Logic Analyzer (ILA) for real-time signal debugging - Implement assertion-based verification to catch protocol violations ## Advanced Techniques ### Clock Domain Crossing - Use synchronizers or FIFOs to handle CDC safely - Implement proper handshaking protocols ### AXI Protocol Compliance - Ensure proper read/write channel management and handshakes - Optimize for high-throughput with proper burst sizing ### DMA Integration - Configure burst transfers for maximum throughput - Handle buffer management efficiently ### Latency Reduction - Implement fine-tuned pipeline stages strategically - Balance latency vs. throughput requirements
© Mindrally · Apache-2.0 · Mindrally/skills
