tailslayer-dram-hedged-reads — Claude Code skill: how to install
Guides coding assistants in setting up C++ hedged reads across DRAM channels. It helps eliminate memory tail latency caused by periodic DRAM refresh pauses.
npx skills add reason-machines/trending-skills --skill tailslayer-dram-hedged-reads -a claude-codeWhat tailslayer-dram-hedged-reads does
This skill teaches coding agents how to integrate the Tailslayer C++ library. Periodic DRAM refresh cycles stall RAM reads and create latency spikes. Tailslayer counters this by storing copies of your data across separate memory channels with out-of-sync refresh timers. Worker threads issue parallel reads to every copy. The earliest channel to reply supplies the value.
Channel routing relies on undocumented scrambling offsets and selection bits. The library works on AMD Zen, Intel architectures, and AWS Graviton servers. Standard configurations use bits 6, 7, or 8, while Graviton targets bit 8. By default, the HedgedReader template handles 2 channel replicas. Exceeding two replicas requires using benchmark programs in discovery/benchmark/.
Running the included trefi_probe and hedged benchmarks requires sudo privileges and real-time scheduling via chrt. Each background reader thread pins directly to a dedicated CPU core with tailslayer::pin_to_core, so thread contention on unpinned cores will break timing guarantees.
What it helps with
- cut DRAM tail latency spikes caused by refresh cycles
- set up hedged memory reads with
tailslayer::HedgedReader - pin reader threads to separate CPU cores
- detect optimal memory channel bits across AMD, Intel, or AWS Graviton
- measure tREFI refresh timing using the
trefi_probeutility
Example prompts for the agent
- Show me how to include
tailslayer/hedged_reader.hppand configure a 2-way hedged reader foruint8_t. - Implement
tailslayer::HedgedReaderpassing custom arguments to signal and work handlers viaArgList. - How do I run the
hedged_read_cppbenchmark with--channel-bit 8usingchrt?
How to install tailslayer-dram-hedged-reads
1Skills CLI (Vercel)
npx skills add reason-machines/trending-skills --skill tailslayer-dram-hedged-reads -a claude-code2Manually: put the files in place
~/.claude/skills/tailslayer-dram-hedged-reads/SKILL.mdCopy the whole skill folder; for one project use .claude/skills/tailslayer-dram-hedged-reads/
1Skills CLI (Vercel)
npx skills add reason-machines/trending-skills --skill tailslayer-dram-hedged-reads -a codex2Manually: put the files in place
.agents/skills/tailslayer-dram-hedged-reads/SKILL.mdFor all projects use ~/.agents/skills/
1Skills CLI (Vercel)
npx skills add reason-machines/trending-skills --skill tailslayer-dram-hedged-reads -a cursor2Manually: put the files in place
.cursor/skills/tailslayer-dram-hedged-reads/SKILL.mdCursor also reads .agents/skills/ and .claude/skills/
1GitHub CLI
gh skill install reason-machines/trending-skills tailslayer-dram-hedged-reads2Manually: put the files in place
.github/skills/tailslayer-dram-hedged-reads/SKILL.md1Skills CLI (Vercel)
npx skills add reason-machines/trending-skills --skill tailslayer-dram-hedged-reads -a gemini-cli2Platform CLI
gemini skills install https://github.com/reason-machines/trending-skills --path skills/tailslayer-dram-hedged-readsManually: put the files in place
.devin/skills/tailslayer-dram-hedged-reads/SKILL.mdThe legacy .windsurf/skills/ path still works
Skills CLI (Vercel)
npx skills add reason-machines/trending-skills --skill tailslayer-dram-hedged-reads -a opencodeClaude.ai
Zip the folder and upload it in Settings → Capabilities → Skills
Step by step, with commands for each platform: How to install skills in Claude Code: five ways
Questions about tailslayer-dram-hedged-reads
How do I install tailslayer-dram-hedged-reads in Claude Code?
Run npx skills add reason-machines/trending-skills --skill tailslayer-dram-hedged-reads -a claude-code in your terminal. This adds the skill instructions to your agent environment.
What problem does DRAM hedged reading solve?
Standard RAM reads stall whenever a DRAM bank enters its tREFI refresh cycle. Hedging sends concurrent read requests across independent channels, ensuring the fastest non-refreshing channel delivers the payload without waiting.
Which processor platforms are compatible with Tailslayer?
The library functions on AMD Zen chips (typically channel bit 6 or 7), Intel systems (bits 6, 7, or 8), and AWS Graviton (bit 8). You can verify the right channel bit for your hardware with the --all benchmark flag.
