Skip to main content
skill CX Codex

virtual-memory-paging-and-tlb — Claude Code skill: usage & install

This skill guides coding agents through virtual memory translation, x86-64 multi-level page tables, and TLB lookups. It helps troubleshoot page faults and huge page tuning.

Install into Claude Code · Skills CLI (Vercel) All methods and platforms ↓
npx skills add mohitmishra786/low-level-dev-skills --skill virtual-memory-paging-and-tlb -a claude-code
Open on GitHub

What virtual-memory-paging-and-tlb does

The skill outlines the translation path from virtual addresses to physical memory frames. It tracks TLB lookups and misses that trigger page table walks through x86-64 structures like PML4, PDPT, PD, and PT. It also covers page fault classification, distinguishing major disk-backed faults from minor copy-on-write splits and memory protection traps.

To inspect active address spaces on Linux, the workflow suggests querying /proc/self/maps, checking pmap -x, or scanning /proc/vmstat for fault counts. High TLB pressure caused by sparse pointer traversal gets resolved by configuring huge pages via MAP_HUGETLB or madvise(MADV_HUGEPAGE).

On Cortex-M microcontrollers, full paging does not exist. They rely on region-based MPUs with static ranges defined in linker scripts. Applying MMU-based translation rules to raw MCUs will produce incorrect physical addresses.

What it helps with

  • diagnose segfaults and W^X permission violations
  • mitigate TLB thrashing with huge pages in mmap workloads
  • categorize minor and major page faults in Linux processes
  • contrast Cortex-M MPU memory regions with MMU page tables

Example prompts for the agent

  • /virtual-memory-paging-and-tlb Explain why 4 KiB random access causes TLB pressure and how huge pages help
  • /virtual-memory-paging-and-tlb How do I inspect memory mappings for this process using /proc/self/maps?
  • /virtual-memory-paging-and-tlb What causes a minor page fault during a copy-on-write operation after fork?

How to install virtual-memory-paging-and-tlb

1Skills CLI (Vercel)

npx skills add mohitmishra786/low-level-dev-skills --skill virtual-memory-paging-and-tlb -a claude-code

2Manually: put the files in place

~/.claude/skills/virtual-memory-paging-and-tlb/SKILL.md

Copy the whole skill folder; for one project use .claude/skills/virtual-memory-paging-and-tlb/

Step by step, with commands for each platform: How to install skills in Claude Code: five ways

Questions about virtual-memory-paging-and-tlb

How to install virtual-memory-paging-and-tlb in Claude Code?

Run npx skills add mohitmishra786/low-level-dev-skills --skill virtual-memory-paging-and-tlb -a claude-code. You can also manually place the skill file at ~/.claude/skills/virtual-memory-paging-and-tlb/SKILL.md.

What does virtual-memory-paging-and-tlb do?

It teaches coding agents to explain address translation, x86-64 page tables, TLB hits and misses, and demand paging in operating systems.

How does the skill handle embedded systems like Cortex-M?

It highlights that Cortex-M microcontrollers use an MPU with fixed regions rather than an MMU with paging, requiring linear address mapping via linker scripts.

Source text

SKILL.md · MIT
---
name: virtual-memory-paging-and-tlb
description: Virtual memory skill for paging, page tables, and TLB. Use when explaining page faults, multi-level page tables, TLB behavior, or virtual vs physical addressing. Activates on queries about virtual memory, page table, TLB, page fault, mmap paging, or x86-64 paging.
---

# Virtual Memory, Paging, and TLB

## Purpose

Explain virtual memory: paging, multi-level page tables, TLB role, page faults, and address translation — bridging OS kernels, embedded MPU, and performance analysis.

## When to Use

- Understanding `mmap`, `brk`, and demand paging
- Debugging segfaults and guard pages
- Huge pages / TLB pressure tuning
- Contrasting Cortex-M MPU with full MMU systems

## Workflow

### 1. Translation overview

```
Virtual address (VA)
├── TLB lookup → physical on hit
└── TLB miss → page table walk → fill TLB
        ├── valid PTE → physical address
        └── invalid → page fault (OS handles)
```

### 2. Page table (x86-64 4-level example)

```
CR3 → PML4 → PDPT → PD → PT → physical frame
```

Linux on x86_64 uses 4 KiB pages (default) and optional 2 MiB / 1 GiB huge pages.

### 3. Page fault types (simplified)

| Fault | Typical cause |
|-------|----------------|
| Major | Disk read — file-backed page not in RAM |
| Minor | Zero-fill or COW break |
| Protection | User access to kernel page, W^X violation |

```bash
# Linux page fault stats
grep pgfault /proc/vmstat
```

### 4. TLB pressure

Large sparse address spaces + random pointer chasing → TLB misses dominate.

Mitigations:

- `mmap` huge pages (`MAP_HUGETLB`, `madvise(MADV_HUGEPAGE)`)
- Smaller working set / better locality
- `numactl --membind` for NUMA

### 5. Embedded contrast (Cortex-M)

Many MCUs use **MPU** (region-based) not full paging — no TLB, fixed region count. Application processors use MMU + OS.

See `skills/platform/riscv-privileged` for Sv39/Sv48.

### 6. Userspace inspection (Linux)

```bash
cat /proc/self/maps
pmap -x $$
```

### 7. Agent usage

```
/virtual-memory-paging-and-tlb Explain why 4 KiB random access hurts TLB and hugepage helps
```

## Common Problems

| Symptom | Cause | Fix |
|---------|-------|-----|
| Segfault | Unmapped VA | Fix pointer; check `maps` |
| Slow mmap workload | TLB thrashing | Huge pages; reduce regions |
| COW spike after fork | Shared pages split on write | Expected; consider `MAP_POPULATE` |
| W^X fault | JIT without mprotect dance | Separate RW and RX mappings |
| Wrong phys on MCU | No MMU — linear map | Use linker script addresses |

## Related Skills

- `skills/computer-architecture/memory-hierarchy-and-caches` — cache after translation
- `skills/kernel-dev/kernel-memory-management` — kernel page allocator
- `skills/kernel/os-dev-scratch` — build paging from scratch
- `skills/platform/riscv-privileged` — Sv39 page tables
- `skills/allocators/numa-programming` — NUMA and migration

© mohitmishra786 · MIT · mohitmishra786/low-level-dev-skills

Similar skills

All skills for Backend and APIs →

From the same set90

Project sponsors

Companies that keep this analytics open
Gold sponsor

Impressions, clicks and code copies — open statistics. We keep the numbers public for the same reason NeBlask itself is public. Become a sponsor