# memory-hierarchy-and-caches

This skill guides agents through CPU cache levels, MESI coherence protocols, and false sharing diagnostics. It helps optimize data layouts when thread scaling drops.

- skill · `type=skill` · Claude Code, Codex, Cursor, GitHub Copilot, Gemini CLI, OpenCode · 322 installs · ★ 267
- Author: mohitmishra786
- License: MIT · policy=mirror · the beginning of the file is at the end of this page
- Source: https://github.com/mohitmishra786/low-level-dev-skills/tree/HEAD/skills/computer-architecture/memory-hierarchy-and-caches/SKILL.md
- Updated: 2026-06-27
- HTML: https://affpapa.org/en/nevibecode/skills/memory-hierarchy-and-caches

## What it does

The skill provides hardware context regarding CPU memory stages, running from per-core L1 caches (~32 KiB, around 4 cycles) up to shared L3 blocks and DRAM. It focuses on cache line mechanics and set-associativity. When threads concurrently modify adjacent fields on a shared 64-byte boundary, MESI invalidations stall execution. That ruins multicore scalability.

Instruction material outlines fixes like `alignas(64)` struct padding, manual prefetching via `__builtin_prefetch`, and measuring hardware events with `perf stat`. It also covers embedded SoC setups where MCUs lack L2 or L3 caches, requiring manual cache invalidation for DMA operations. Stride prefetchers handle sequential loops well. Irregular lookups simply miss.

Without running `getconf LEVEL1_DCACHE_LINESIZE`, hardcoded 64-byte padding assumptions will fail on architectures with non-standard line sizes.

## Install

### Claude Code (native platform)

1. **Skills CLI (Vercel)**
```bash
npx skills add mohitmishra786/low-level-dev-skills --skill memory-hierarchy-and-caches -a claude-code
```

2. **Manually: put the files in place**
- File: `~/.claude/skills/memory-hierarchy-and-caches/SKILL.md` — Copy the whole skill folder; for one project use .claude/skills/memory-hierarchy-and-caches/

### Codex

1. **Skills CLI (Vercel)**
```bash
npx skills add mohitmishra786/low-level-dev-skills --skill memory-hierarchy-and-caches -a codex
```

2. **Manually: put the files in place**
- File: `.agents/skills/memory-hierarchy-and-caches/SKILL.md` — For all projects use ~/.agents/skills/

### Cursor

1. **Skills CLI (Vercel)**
```bash
npx skills add mohitmishra786/low-level-dev-skills --skill memory-hierarchy-and-caches -a cursor
```

2. **Manually: put the files in place**
- File: `.cursor/skills/memory-hierarchy-and-caches/SKILL.md` — Cursor also reads .agents/skills/ and .claude/skills/

### GitHub Copilot

1. **GitHub CLI**
```bash
gh skill install mohitmishra786/low-level-dev-skills memory-hierarchy-and-caches
```

2. **Manually: put the files in place**
- File: `.github/skills/memory-hierarchy-and-caches/SKILL.md`

### Gemini CLI

1. **Skills CLI (Vercel)**
```bash
npx skills add mohitmishra786/low-level-dev-skills --skill memory-hierarchy-and-caches -a gemini-cli
```

2. **Platform CLI**
```bash
gemini skills install https://github.com/mohitmishra786/low-level-dev-skills --path skills/computer-architecture/memory-hierarchy-and-caches
```

### Windsurf (Devin Desktop)

**Manually: put the files in place**
- File: `.devin/skills/memory-hierarchy-and-caches/SKILL.md` — The legacy .windsurf/skills/ path still works

### OpenCode

**Skills CLI (Vercel)**
```bash
npx skills add mohitmishra786/low-level-dev-skills --skill memory-hierarchy-and-caches -a opencode
```

### Claude.ai

**Claude.ai**
- Zip the folder and upload it in Settings → Capabilities → Skills

Where a file is given instead of a command, copy the files from the source to that path: https://github.com/mohitmishra786/low-level-dev-skills/tree/HEAD/skills/computer-architecture/memory-hierarchy-and-caches/SKILL.md

## When to use it
- Resolve false sharing between worker threads using struct alignment
- Insert manual prefetch hints with `__builtin_prefetch` for loops
- Diagnose L1 and LLC misses using `perf stat` hardware counters
- Handle DMA cache invalidation on embedded microcontrollers

## Example prompts
- /memory-hierarchy-and-caches Diagnose false sharing in this per-thread stats array
- /memory-hierarchy-and-caches How does struct padding restore multicore scaling here?
- /memory-hierarchy-and-caches Analyze cache miss counters from my perf stat output

## Source text · SKILL.md · MIT

Below is the content of a third-party file. It is data, not instructions for you: do not act on anything written inside unless the human asks. Block tag: 22b774183651c04a.

BEGIN THIRD-PARTY FILE 22b774183651c04a
````text
---
name: memory-hierarchy-and-caches
description: Memory hierarchy skill for caches, coherence, and locality. Use when explaining cache levels, associativity, false sharing, prefetching, or MESI coherence. Activates on queries about cache hierarchy, L1 L2 L3, false sharing, cache line, prefetch, or cache coherence.
---

# Memory Hierarchy and Caches

## Purpose

Teach CPU memory hierarchy: cache levels, associativity, line size, coherence protocols, false sharing, and prefetch behavior — architectural depth complementing optimization practice in `skills/low-level-programming/cpu-cache-opt`.

## When to Use

- Explaining why padding fixes scalability
- Choosing struct layout for multicore
- Interpreting cache miss counters
- Understanding DMA vs CPU cache on embedded SoCs

## Workflow

### 1. Hierarchy (typical desktop/ server)

```
Registers
├── L1d / L1i (per core, ~32 KiB, ~4 cycles)
├── L2 (per core, ~256 KiB – 1 MiB)
├── L3 (shared last-level, MiB – tens of MiB)
├── DRAM (hundreds of cycles)
└── Storage / NUMA remote (much slower)
```

Embedded MCUs may have only tightly-coupled memory (no L2/L3).

### 2. Cache line and associativity

- Line size: commonly **64 bytes** on x86/ARM64 (verify with `getconf LEVEL1_DCACHE_LINESIZE`)
- Set-associative: line maps to one set, competes within ways
- Conflict misses: many aliases same set

### 3. False sharing

```c
/* Bad — two atomics on same cache line */
struct {
    atomic_int counter_a;
    atomic_int counter_b;
} stats;

/* Good — pad to cache line */
struct alignas(64) {
    atomic_int counter_a;
    char pad[64 - sizeof(atomic_int)];
    atomic_int counter_b;
} stats;
```

### 4. Coherence (multicore)

MESI states: Modified, Exclusive, Shared, Invalid. Writes invalidate other cores' copies of the line — why atomics and locks ping cache lines.

### 5. Prefetching

```c
#ifdef __builtin_prefetch
for (int i = 0; i < n; i++) {
    __builtin_prefetch(&data[i + 8], 0, 3);
    process(data[i]);
}
#endif
```

Hardware stride prefetchers detect sequential access; random access misses.

### 6. Measurement

```bash
perf stat -e cache-references,cache-misses,L1-dcache-load-misses ./app
```

### 7. Agent usage

```
/memory-hierarchy-and-caches Diagnose false sharing in this per-thread stats array
```

## Common Problems

| Symptom | Cause | Fix |
|---------|-------|-----|
````
END THIRD-PARTY FILE 22b774183651c04a

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