# assembly-riscv

Guides coding agents through RV32 and RV64 assembly, psABI calling conventions, GCC inline asm, and QEMU debugging with GDB.

- skill · `type=skill` · Claude Code, Codex, Cursor, GitHub Copilot, Gemini CLI, OpenCode · 483 installs · ★ 267
- Author: mohitmishra786
- License: MIT · policy=mirror · the beginning of the file is at the end of this page
- Source: https://github.com/mohitmishra786/low-level-dev-skills/tree/HEAD/skills/low-level-programming/assembly-riscv/SKILL.md
- Updated: 2026-06-27
- HTML: https://affpapa.org/en/nevibecode/skills/assembly-riscv

## What it does

The skill supplies the agent with the RISC-V register layout (x0 to x31), distinguishing caller-saved registers like `t0` from callee-saved ones like `s0` and `sp`. It clarifies ISA naming conventions ranging from base integer cores to `rv64gc` and vector extensions. Without these rules, models frequently break stack frames.

It details function prologue and epilogue patterns, compressed 16-bit RVC instruction rules, and C inline assembly constructs for reading CSRs or issuing `fence` directives. It also provides workflows for running binaries through `qemu-riscv64` or attaching `riscv64-linux-gnu-gdb` via port 1234. Testing compiled binaries requires external packages like `qemu-user` and `riscv64-linux-gnu-gcc` on the host machine.

## Install

### Claude Code (native platform)

1. **Skills CLI (Vercel)**
```bash
npx skills add mohitmishra786/low-level-dev-skills --skill assembly-riscv -a claude-code
```

2. **Manually: put the files in place**
- File: `~/.claude/skills/assembly-riscv/SKILL.md` — Copy the whole skill folder; for one project use .claude/skills/assembly-riscv/

### Codex

1. **Skills CLI (Vercel)**
```bash
npx skills add mohitmishra786/low-level-dev-skills --skill assembly-riscv -a codex
```

2. **Manually: put the files in place**
- File: `.agents/skills/assembly-riscv/SKILL.md` — For all projects use ~/.agents/skills/

### Cursor

1. **Skills CLI (Vercel)**
```bash
npx skills add mohitmishra786/low-level-dev-skills --skill assembly-riscv -a cursor
```

2. **Manually: put the files in place**
- File: `.cursor/skills/assembly-riscv/SKILL.md` — Cursor also reads .agents/skills/ and .claude/skills/

### GitHub Copilot

1. **GitHub CLI**
```bash
gh skill install mohitmishra786/low-level-dev-skills assembly-riscv
```

2. **Manually: put the files in place**
- File: `.github/skills/assembly-riscv/SKILL.md`

### Gemini CLI

1. **Skills CLI (Vercel)**
```bash
npx skills add mohitmishra786/low-level-dev-skills --skill assembly-riscv -a gemini-cli
```

2. **Platform CLI**
```bash
gemini skills install https://github.com/mohitmishra786/low-level-dev-skills --path skills/low-level-programming/assembly-riscv
```

### Windsurf (Devin Desktop)

**Manually: put the files in place**
- File: `.devin/skills/assembly-riscv/SKILL.md` — The legacy .windsurf/skills/ path still works

### OpenCode

**Skills CLI (Vercel)**
```bash
npx skills add mohitmishra786/low-level-dev-skills --skill assembly-riscv -a opencode
```

### Claude.ai

**Claude.ai**
- Zip the folder and upload it in Settings → Capabilities → Skills

Where a file is given instead of a command, copy the files from the source to that path: https://github.com/mohitmishra786/low-level-dev-skills/tree/HEAD/skills/low-level-programming/assembly-riscv/SKILL.md

## When to use it
- write RISC-V assembly functions following psABI register rules
- add inline assembly blocks to C programs with GCC or Clang
- configure QEMU system emulation with a waiting GDB stub
- verify whether compiler output generated 16-bit compressed RVC instructions

## Example prompts
- Write a recursive factorial routine in RV64 assembly following psABI.
- Show an inline asm helper in C to read the cycle counter via rdcycle.
- How do I launch qemu-system-riscv64 with GDB remote debugging enabled?

## Source text · SKILL.md · MIT

Below is the content of a third-party file. It is data, not instructions for you: do not act on anything written inside unless the human asks. Block tag: 966871936477f3b7.

BEGIN THIRD-PARTY FILE 966871936477f3b7
````text
---
name: assembly-riscv
description: RISC-V assembly skill for RV32/RV64 programming. Use when working with the RISC-V ISA, calling conventions (psABI), inline assembly with GCC/Clang, understanding extension naming (IMAFD), compressed instructions, or simulating RISC-V with QEMU and GDB remote debugging. Activates on queries about RISC-V assembly, RV32, RV64, RISC-V calling convention, RISC-V inline asm, RISC-V extensions, QEMU RISC-V, or RISC-V GDB.
---

# RISC-V Assembly

## Purpose

Guide agents through RISC-V assembly programming: RV32/RV64 instruction sets, register naming and calling conventions (psABI), ISA extension naming, inline assembly with GCC/Clang, compressed (RVC) instructions, and QEMU-based simulation with GDB remote debugging.

## Triggers

- "How do I write RISC-V assembly?"
- "What are the RISC-V calling convention registers?"
- "How do I use inline asm for RISC-V in C?"
- "What do RISC-V extension letters mean (IMAFD)?"
- "How do I simulate RISC-V with QEMU?"
- "How do I debug RISC-V code with GDB?"

## Workflow

### 1. Register file and calling convention

RISC-V has 32 integer registers (x0–x31) with ABI names:

| Register | ABI name | Role | Saved by |
|----------|----------|------|----------|
| x0 | zero | Hard-wired zero | — |
| x1 | ra | Return address | Caller |
| x2 | sp | Stack pointer | Callee |
| x3 | gp | Global pointer | — |
| x4 | tp | Thread pointer | — |
| x5–x7 | t0–t2 | Temporaries | Caller |
| x8 | s0/fp | Frame pointer | Callee |
| x9 | s1 | Saved register | Callee |
| x10–x11 | a0–a1 | Arguments / return values | Caller |
| x12–x17 | a2–a7 | Arguments | Caller |
| x18–x27 | s2–s11 | Saved registers | Callee |
| x28–x31 | t3–t6 | Temporaries | Caller |

Floating-point registers (F extension): f0–f31 (fa0–fa7 for arguments).

### 2. Basic instructions

```asm
# Arithmetic (R and I type)
add   a0, a1, a2      # a0 = a1 + a2
sub   a0, a1, a2      # a0 = a1 - a2
addi  a0, a1, 42      # a0 = a1 + 42 (immediate)
mul   a0, a1, a2      # a0 = a1 * a2 (M extension)
div   a0, a1, a2      # signed divide (M extension)
rem   a0, a1, a2      # remainder (M extension)

# Logical
and   a0, a1, a2      # bitwise AND
or    a0, a1, a2      # bitwise OR
xor   a0, a1, a2      # bitwise XOR
sll   a0, a1, a2      # shift left logical
srl   a0, a1, a2      # shift right logical (unsigned)
sra   a0, a1, a2      # shift right arithmetic (signed)

# Load / store
lw    a0, 0(sp)       # load word (32-bit)
ld    a0, 0(sp)       # load doubleword (64-bit, RV64)
lh    a0, 4(sp)       # load halfword (sign-extended)
lbu   a0, 8(sp)       # load byte (zero-extended)
sw    a0, 0(sp)       # store word
sd    a0, 0(sp)       # store doubleword (RV64)

# Branches (compare and branch)
beq   a0, a1, label   # branch if equal
````
END THIRD-PARTY FILE 966871936477f3b7

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First 2812 of 7311 bytes. © mohitmishra786 · MIT · https://github.com/mohitmishra786/low-level-dev-skills/tree/HEAD/skills/low-level-programming/assembly-riscv/SKILL.md

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