# xilinx-suite

Turns a plain-language description of your design into runnable Tcl, XDC, shell scripts and C/C++ templates for Vivado, Vitis HLS, Vitis Unified and PetaLinux.

- plugin · `type=plugin` · Claude Code · ★ 479
- Author: QingquanYao
- License: not stated · policy=link-only · description only; the file stays with the author
- Source: https://github.com/QingquanYao/xilinx-skill/tree/HEAD/plugins/xilinx-suite
- Updated: 2026-04-25
- HTML: https://affpapa.org/en/nevibecode/plugins/xilinx-suite

## What it does

The plugin covers the flow from an HLS algorithm to a boot image. Describe what you want to build, and the skill asks about your target device, tool version and interfaces, pulls the matching reference doc, then hands you a script you can run.

It ships a reference library: `vivado_guide.md`, `mpsoc_ps_config.md`, `xdc_constraints.md`, `hls_guide.md`, `vitis_unified_guide.md`, `petalinux_guide.md`, `jesd204b_to_c_migration.md`, `vu9p_guide.md`, `tcl_commands.md`, plus an index of official Xilinx/AMD documentation. The JESD204B to 204C migration notes cover port mapping and register differences.

Full automation needs the MCP servers: `vivado-mcp`, `vitis_mcp`, `ssh-mcp` and `vmware-mcp`. Without them the skill writes scripts but does not drive the tools. Claude installs it from the plugin marketplace; Codex and OpenClaw use `install.sh` or a manual copy of `SKILL.md` and `references`.

## Install

### Claude Code (native platform)

**Plugin marketplace**
In the agent chat (not a shell):
```text
/plugin marketplace add anthropics/claude-plugins-community
```
In the agent chat (not a shell):
```text
/plugin install xilinx-suite@claude-community
```

## When to use it
- build a Vivado project with PS, AXI GPIO and a BRAM controller
- generate 200 MHz XDC constraints with the LVDS IO standard
- produce a PetaLinux image from an XSA with a device tree overlay
- migrate a JESD204B DAC interface to JESD204C
- create a matrix multiply HLS IP with AXI4-Stream

## Example prompts
- Create a Vivado project for my ZynqMP board with Zynq PS, 2 AXI GPIO and a BRAM controller
- Generate XDC constraints for my Virtex UltraScale+ board with a 200MHz system clock and LVDS IO standard
- Build a PetaLinux image from my XSA file, I need a custom device tree overlay

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