# neosyn-fpga-mcp

Connect an AI coding agent to the C⏚ FPGA toolchain to check source code, run simulations, and produce Verilog for hardware development.

- MCP server · `type=mcp` · Claude Code, Codex, Cursor, GitHub Copilot, Windsurf (Devin Desktop), Cline, Zed, Gemini CLI · ★ 1
- Author: Neosyn-Logic
- License: MIT · policy=link-only · description only; the file stays with the author
- Source: https://github.com/Neosyn-Logic/cg-agent-kit
- Updated: 2026-10-21
- HTML: https://affpapa.org/en/nevibecode/mcp/neosyn-fpga-mcp

## What it does

neosyn-fpga-mcp exposes C⏚ compiler and verification functions to AI agents over MCP. The agent can inspect compiler diagnostics, simulate a design, and generate Verilog files. Its `cg_synth` tool runs synthesis through Yosys, returning findings that help identify constant-folded logic or inferred latches.

The server works alongside `cg_context.md`, a language reference pack covering C⏚ types, ports, structures, and other language details. For a new design, `cg_scaffold` creates a compiling, self-checking starting structure with unfinished logic sections. A practical workflow is to compile first, simulate the design, and then inspect its synthesis results.

You need Python 3.10+, Java 17 or newer on `PATH`, and a C⏚ compiler JAR configured through `CG_JAR`. Install Yosys on `PATH` to use `cg_synth`; `iverilog` is needed when selecting the Icarus Verilog simulator. The bytecode simulator comes with the commercial distribution, which also requires a licence file configured through `NEOSYN_CG_LICENSE` or stored at the extension's default location.

## Requirements
- Needs: Python and uv (commands run via uvx)
- Environment variables: `CG_JAR` — keys and tokens: ask the human for the values, never commit them or put them in shared files.

## Install

### Claude Code (native platform)

**Platform CLI**
```bash
claude mcp add --env CG_JAR=<CG_JAR> --transport stdio neosyn-fpga-mcp -- uvx neosyn-fpga-mcp
```
Replace <…> with your own values. uvx runs the command named after the package; if the README names another one, use uvx --from neosyn-fpga-mcp <command>

### Codex

**Platform CLI**
```bash
codex mcp add neosyn-fpga-mcp --env CG_JAR=<CG_JAR> -- uvx neosyn-fpga-mcp
```
Replace <…> with your own values. uvx runs the command named after the package; if the README names another one, use uvx --from neosyn-fpga-mcp <command>

### Cursor

**Config file**
File `.cursor/mcp.json`:
```json
{
    "mcpServers": {
        "neosyn-fpga-mcp": {
            "command": "uvx",
            "args": [
                "neosyn-fpga-mcp"
            ],
            "env": {
                "CG_JAR": "<CG_JAR>"
            }
        }
    }
}
```
Replace <…> with your own values. uvx runs the command named after the package; if the README names another one, use uvx --from neosyn-fpga-mcp <command>

### GitHub Copilot

**Config file**
File `.vscode/mcp.json`:
```json
{
    "servers": {
        "neosyn-fpga-mcp": {
            "type": "stdio",
            "command": "uvx",
            "args": [
                "neosyn-fpga-mcp"
            ],
            "env": {
                "CG_JAR": "<CG_JAR>"
            }
        }
    }
}
```
Replace <…> with your own values. uvx runs the command named after the package; if the README names another one, use uvx --from neosyn-fpga-mcp <command>

### Gemini CLI

**Platform CLI**
```bash
gemini mcp add -e CG_JAR=<CG_JAR> neosyn-fpga-mcp uvx neosyn-fpga-mcp
```
Replace <…> with your own values. uvx runs the command named after the package; if the README names another one, use uvx --from neosyn-fpga-mcp <command>

## When to use it
- Inspect C⏚ source code and resolve compiler diagnostics
- Simulate hardware behavior and check output values
- Generate Verilog files for an RTL workflow
- Detect constant-folded logic or inferred latches during synthesis
- Create a self-checking scaffold for a task, FSM, or stream

## Example prompts
- Check this C⏚ source with `cg_check` and fix the reported compiler issues.
- Run `cg_simulate` on this hardware design and verify its outputs across test cycles.
- Generate Verilog with `cg_generate_verilog`, then inspect the synthesis results using `cg_synth`.

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